The SPARC chip family includes several successive levels (or other variants) of chip, using the same core instruction set, but including a few additional instructions at each level.
By default, as
assumes the core instruction set (SPARC
v6), but "bumps" the architecture level as needed: it switches to
successively higher architectures as it encounters instructions that
only exist in the higher levels.
If not configured for SPARC v9 (sparc64-*-*
) GAS will not bump
passed sparclite by default, an option must be passed to enable the
v9 instructions.
GAS treats sparclite as being compatible with v8, unless an architecture is explicitly requested. SPARC v9 is always incompatible with sparclite.
-Av6 | -Av7 | -Av8 | -Asparclite | -Av9 | -Av9a
as
reports a fatal error if it encounters an instruction
or feature requiring a higher level.
-xarch=v8plus | -xarch=v8plusa
-bump
The Sparc uses IEEE floating-point numbers.
The Sparc version of as
supports the following additional
machine directives:
.align
.common
"bss"
. This behaves somewhat like .comm
, but the
syntax is different.
.half
.short
.
.proc
.reserve
"bss"
. This behaves somewhat like .lcomm
, but the
syntax is different.
.seg
"text"
, "data"
, or
"data1"
. It behaves like .text
, .data
, or
.data 1
.
.skip
.space
directive.
.word
.word
directive produces 32 bit values,
instead of the 16 bit values it produces on many other machines.
.xword
.xword
directive produces
64 bit values.